The SDSoCâ„¢ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous ZynqÂ® All Programmable SoC and MPSoC deployment.
It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment
Based on the Xilinx UltraScale MPSoC architecture, the Zynq UltraScale+ MPSoCs enable extensive system level dif...
Innovative ARMÂ® + FPGA architecture for differentiation, analytics & control
Multiple levels of hardware and software security
System level performance through optimized architecture
Most flexible & scalable platform for maximum reuse and best TTM
Silicon Devices - Zynq UltraScale+ MPSoC Fully-Featured Processing Platform; Development Platforms - Traditional hardware development and virtual development platforms*; Operating Systems - Open Source Linux, and FreeRTOS*; Design Tools - VivadoÂ® Design Suite, Xilinx SDK, PetaLinux SDK; IP - Plug and Play*
The Xilinx Zynq-7000 EPP ZC702 Video and Imaging Kit builds on the ZC702 Evaluation Kit by including hardware, s...
ZC702 Base Board - ROHS compliant ZC702 kit including the XC7Z020-CLG484-1 EPP; IR cut filter; 12V wall adapter or ATX; Voltage and current measurement capability of supplies; XADC header; AMS evaluation board; Video FMC board with HDMI Input, HDMI Output, and Image Sensor input
Communication & Networking - GigE RGMII Ethernet (PS) ; USB OTG 1 (PS) - Host USB; IIC Bus Headers/HUB (PS); 1 CAN with Wake on CAN (PS); USB UART (PS)
Expansion Connectors â€“ FMC #1-LPC connector (0 GTX Transceiver, 68 single-ended or 34 differential user defined signals); FMC #2-LPC connector (0 GTX Transceiver, 68 single-ended or 34 differential user defined signals); IIC HUB/Expander; Dual Pmod (8 I/O Shared with LED’s); Single Pmod (4 I/O Shared with PJTAG)
Control & I/O - 3 User Push Buttons; 2 User Switches; 8 User LEDs
Offering twice the performance and cutting power consumption makes the Xilinx Kintex-7 FPGAs the clear choice fo...
Many performance boosting innovations, including industry-leading 1,866 Mbps memory interface; 639 MHz DSP48E1 slices with high-performance filtering capabilities, combine with the six-input
look-up table for flexible DSP designs
Uses a 2.5D technique with four 28 nm FPGA die are attached in close proximity on a passive silicon interposer, enabling more than 10,000 high-bandwidth die-to-die interconnections while reducing the power consumed by package-to-package I/O on a printed circuit board by a factor of 100x
A total of 36 Xilinx GTX transceivers are available in the 2000T, with a peak transceiver speed of 12.5 Gbps
Contains 46.5 Mb of block random-access memory (BRAM)
ISE Design Suite 13 maximizes productivity by leveraging open industry standards to accelerate design creation, ...
Accelerated Verification: Leveraging Xilinx's large portfolio of development boards, kits, and Xilinx's ISE Simulator new hardware Co-Simulation, verification engineers can test implemented blocks of the design while leaving blocks under development in the simulator, accelerating overall verification by up to 100 times faster than native simulation
Design Analysis:PlanAhead accelerates time to production with an integrated front-to-back environment with design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis, place, and route. The end result is rapid convergence on power consumption, resource utilization, and performance with fewer time-consuming design iterations
Enhanced Optimizations: Advanced optimizations, including intelligent clock gating that provides up to 30 percent dynamic power reduction, facilitates faster timing closure and timing preservation, increasing overall productivity and reducing design iterations
Plug-and-Play IP ‚Äì The new AMBA¬Æ 4 AXI-4 interconnect protocol IP enables design teams to easily cust...
Design Analysis – PlanAhead accelerates time to production with an integrated front-to-back environment with design analysis at each phase of the design cycle – RTL development, IP integration, verifi cation, synthesis, place, and route; The end result is rapid convergence on power consumption, resource utilization, and performance with fewer time-consuming design iterations
Enhanced Optimizations – Advanced optimizations, including intelligent clock gating that provides up to 30 percent dynamic power reduction, facilitates faster timing closure and timing preservation, increasing overall productivity and reducing design iterations
Xilinx FPGAs exceed the computing power of DSPs with their inherent parallelism and offer co-processing methods ...
The Xilinx Spartan-6 FPGA DSP Kit integrates hardware, IP, software development tools and methodologies together into solutions that accelerate development for experienced users and simplify the adoption of FPGAs for new users
With the addition of targeted reference designs, these DSP platforms enable users to focus on creating their own unique differentiation from the very beginning of the product development process
Traditional RTL design methodologies are also supported through a design implementation that uses ISE Design Suite: Logic Edition and LogicCore DSP IP
Provides a platform for next generation products that include digital signal processing (DSP) which need to deli...
Includes a Xilinx ML605 development board including a Virtex-6 LX240T FPGA, design tools, IP, reference designs, and documentation
Supports both traditional RTL and high-level design methodologies and can easily extended to include additional high-level design flows and I/O daughter cards through third party partners and standardized integration
ISE Design Suite 11 Embedded Edition delivers base-level FPGA features and technologies, plus all the embedded t...
Software Developers Kit (SDK) as stand-alone configuration: Eclipse-based software development environment for feature-rich C/C++ code editing and compilation, source code version control, and seamless debug and profiling of embedded targets