Error Correction Cores

By Altera Corporation

A family of nine high-speed cores built around Altera's new Reed-Solomon Compiler, Viterbi Decoder, and Turbo Encoder/Decoder which are all delivered with Altera's MegaWizard GUI application interface

FEATURES

  • Cores can be used to do functional simulation, using VHDL and Verilog simulators
  • A bit-accurate compiled C model is available for system-level simulation to calculate bit error rates
  • Supports data rates in excess of 2 Mbits/sec
  • Cores can be parameterized and verified with Altera's Quartus or MAX+PLUS II development tools, prior to licensing

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