28-nm Stratix V FPGAs

By Altera Corporation

With the variable-precision DSP block, Altera's Stratix V FPGA can support on a block-by-block basis various precisions ranging from 9-bit x 9-bit up to single-precision floating point (mantissa multiplication) within a single DSP block

28-nm Stratix V FPGAs

FEATURES

  • This frees you from FPGA architecture restrictions, allowing you to use the optimum precision at each stage of the DSP data path
  • Increased system performance, reduced power consumption, and reduced architectural constraints
  • Each variable-precision block can be configured at compile time to implement: Dual 18-bit x 18-bit multipliers in the 'sum' or 'independent' modes
  • A single 27-bit x 27-bit (or 18-bit x 36-bit) multiplier
  • Pre-adder, systolic output adder, and internal coefficient banks supported in both modes
  • All modes feature a 64-bit accumulator, and each variable precision DSP block comes with a 64-bit cascade bus that allows implementation of even higher precision signal processing by cascading multiple blocks using a dedicated bus
  • Variable-precision DSP architecture maintains backward compatibility, so it can efficiently support existing 18-bit DSP applications, such as high-definition video processing, digital up/down conversion, and multi-rate filtering
  • Built for bandwidth
  • High bandwidth I/O
  • Up to 66 high-speed transceivers (1.6 Tbps)
  • 12.5-Gbps backplane and 28-Gbps chip-to-chip
  • Up to 7 x 72-bit 1,600 Mbps DDR3 interface
  • High-performance core
  • Up to 1.1M logic elements
  • Increased storage capacity to 53-Mbit RAM
  • High-performance, variable-precision DSP with up to 3,680 18 x 18 multipliers (1,840 GMACS)
  • Application-targeted hard IP
  • 350 MHz core performance
  • 3rd Generation Programmable Power Technology
  • 30% lower total power than previous generations
  • 28-Gbps transceivers at 200 mW/channel
  • HardCopy V ASIC provides risk-free path to ASIC

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