EP4SE820

By Altera Corporation

Are the engineers at Altera perfectionists? We donít know, but considering their latest attempt to improve upon a good thing, perfectionism could be a distinct possibility. And their most recent FPGA incarnation (or perhaps iteration) proves this point: the newest member of the 40 nm Stratix IV E family, the EP4SE820. Providing a density increase of 53 percent over Alteraís EP4SE530 FPGA, Altera says the deviceís 820 K logic elements set an ìindustry leadingî benchmark. Military, wireless, wireline, and storage apps, in addition to ASIC emulation and prototyping, are the beneficiaries. And though the logic elements are impressive, the story doesnít stop there. High-end digital apps are also benefitted by the EP4SE820ís 650 K registers and 600 MHz embedded memory (23.1 Mb). As if that werenít enough, speeding through the EP4SE820 at 550 MHz are 18 x 18 multipliers (960 of them). The device also boasts 1.25 Bbps LVDS and 1,120 I/0s to ease use. However, some might still wonder about FPGAsí infamous long development timeframes. In the case of the EP4SE820C, compatibility with Alteraís Quartus II design software including ìadvanced place-and-route algorithms,î among other features, makes shorter FPGA development times a reality.

EP4SE820

FEATURES

  • Altera's newest member of the 40 nm Stratix IV E family
  • Density increase of 53 percent over Altera's EP4SE530 FPGA
  • 820 K logic elements
  • Benefits military, wireless, wireline, storage apps,ASIC emulation and prototyping, and high-end digital apps
  • 650 K registers and 600 MHz embedded memory (23.1 Mb)
  • 18 x 18 multipliers (960) at 550 MHz
  • 1.25 Bbps LVDS and 1,120 I/Os
  • The EP4SE820C is compatible with Altera's Quartus II design software including “advanced place-and-route algorithms," among other features, which makes shorter FPGA development times a reality

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