Cyclone III FPGAs

By Altera Corporation


  • Lowest power 65-nm FPGA
  • Manufactured using TSMC's 65-nm low-power (LP) process technology
  • Core static power as low as 35 mW at 25 ºC junction temperature
  • Unused I/O banks can be powered down via support for hot-socketing operation
  • Low-power benefits include: elimination or reduction in cooling system costs, easier thermal management, and extended battery life for portable applications
  • Staggered I/O ring to reduce die size and board space Wide selection of low-cost packages
  • Support for low-cost serial flash and parallel flash configuration devices
  • Complete system integration
  • Up to 120,000 logic elements (1.7 times the density of Cyclone II FPGAs)
  • Up to 4 Mbits of embedded memory (3.5 times more than Cyclone II FPGAs)
  • 260 MHz multiplier performance with the highest multiplier-to-logic ratio in the industry
  • Robust clock management and synthesis with dynamically reconfigurable and flexible phase-locked loops (PLLs)
  • Improved signal integrity with adjustable I/O slew rates Support for high-speed external memory interfaces including DDR, DDR2, SDR SDRAM, and QDRII SRAM with an autocalibrating PHY for fast timing closure Support for I/O standards including LVTTL, LVCMOS, SSTL, HSTL, PCI Express, LVPECL, LVDS, mini-LVDS, RSDS, and PPDS

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