By Curtiss-Wright

The CHAMP-WB-A25G couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with a high-bandwidth 25 GS/s 8-bit ADC module in a commercial grade 6U OpenVPX (VITA 65) form factor module. The 25G ADC module can also operate in a dual channel 12.5 GS/s mode. The CHAMP-WB-A25G complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO (SRIO) or Aurora up to 10.3 Gbps.

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  • 6U OpenVPX Wideband Receiver with 25 GS/s ADC
  • Onboard PCIe Gen3 switch
  • Single user-programmable Xilinx Virtex-7 FPGAs X690T, with 8 GB DDR3L SDRAM
  • OpenVPX (VITA 65) MOD6-PER-4F-12.3.1-8; MOD6-PER-1Q-12.3.5-2 VPX REDI (VITA 48 option)
  • 20 x backplane SerDes capable of 10.3 Gbps each

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