HardCopy II

By Altera Corporation


  • Structured ASICs that deliver an FPGA prototype to structured ASIC design flow
  • Up to 350 MHz system performance, 2.2 million ASIC gates, and 8.8 Mb of RAM
  • Up to 50 percent faster with less than half the power consumption of FPGA prototype
  • Dedicated DSP functionality providing up to 384 18 x 18 multipliers
  • High-speed differential I/O supporting data rates up to 1 Gbps and I/O interfaces such as LVDS, LVPECL, and HyperTransport
  • DPA circuitry that simplifies PCB layout by eliminating signal alignment issues due to source-synchronous signaling
  • Supports high-bandwidth, single-ended I/O standards, including SSTL, HSTL, PCI, and PCI-X
  • Advanced external-memory interfaces for integrating external SRAM and DRAM without degrading performance
  • Minimizes external resistors with on-chip series and differential termination
  • Fully supported by Altera's Quartus II software and industry standard EDA tool flows

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