Nios II, Stratix

By Altera Corporation

Nios II, Stratix


  • Internal clock frequency rates up to 500 MHz and typical performance >250 MHz
  • Deliver on average 50% faster performance and more than 2x the logic capacity than first-generation Stratix FPGAs
  • Deliver 50x higher multiplier bandwidth than single-chip, standalone digital signal processors
  • The DSP blocks have the flexibility and performance to implement fast, arithmetic-intensive applications such as image processing, wireless communications, military, broadcast, and medical
  • Each DSP block has dedicated multiwidth multipliers to implement DSP algorithms and functions, including filtering, video and image processing, correlation, transforms, encryption, and error correction
  • Offers Intellectual Property (IP) cores to speed development, including three Nios II 32-bit RISC processors
  • Optimized for a specific price and performance range, allowing designers to choose a system configuration that is an exact fit for their embedded needs
  • Upgrade system performance at any stage of the product life cycle without having to redesign the board or develop hand-optimized software
  • All three processors use the same instruction set architecture and are 100 percent binary code compatible
  • Can be added to a designer's system using the SOPC Builder system development tool in the Quartus II development software
  • The Nios II C-to-Hardware Acceleration (C2H) Compiler boosts performance of time-critical C subroutines, converting them to powerful hardware accelerators with a simple “right-click to accelerate" interface
  • This kit includes 12 months of upgrades
  • This development kit is now RoHS-compliant.

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