ARM-based SoC FPGA Family

By Altera Corporation

Provides users with single-chip solutions that integrate an industrial-grade dual-core 800 MHz ARM Cortex-A9 processor with Altera's 28 nm low-power Cyclone V and Arria V FPGAs

ARM-based SoC FPGA Family
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  • Each core in the Altera SoC FPGA processor system includes a ARM NEON media processing engine and a single/double- precision floating point unit with 32 KB/32 KB (instruction/data) of L1 cache per core
  • The pair of processors shares an Error Correcting Code (ECC) protected 512 KB L2 cache
  • Additional hard IP in the SoC FPGAs will include up to three multiport memory controllers with ECC for DDR2/3, Mobile DDR, and LPDDR2 memories
  • For flash memories, the SoC FPGAs include a Queued Serial Peripheral Interface (QSPI) for NOR and a NAND controller, both with ECC
  • The SoC FPGAs also provide up to two PCIe Gen 2 x4 interfaces as hard IP and soft IP is available for users who require PCIe x8 configurations

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